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| Standard ICs 8-bit shift register and latch driver BU2114 / BU2114F The BU2114 and BU2114F are CMOS ICs with low power consumption, and are equipped with an 8-bit shift register latch. Data in the shift register can be latched asynchronously. The outputs (O1 to O8) are open drain outputs (because there is no protection diode, a maximum voltage above VDD, of up to 7V, can be applied), and one output can drive 36 mA. A total output of up to 150 mA can be driven (when using static operation). *Applications for a wide range of applications in microcomputer peripheral circuits, such as in industrial equipThese are designed ment, office telephones, audio visual equipment, and expansion input and output boards. *Features configuration enables low power con1) The CMOS sumption. 2) Open drain output. 3) Latch to 8-bit shift register provided, enabling drive of up to 150mA. (ISINK = 36mA) 4) Cascade connections possible. *Absolute maximum ratings (unless otherwise noted, Ta = 25C) Parameter Applied voltage Input voltage Operating temperature Storage temperature Input protection diode current Power dissipation BU2114 BU2114F Symbol VDD VIN Topr Tstg ID Pd Limits - 0.3 ~ + 7.0 - 0.3 ~ VDD0.3 - 25 ~ + 75 - 55 ~ + 150 20 11001 4002 Unit V V C C mA mW 1 Power dissipation is reduced by 8.8mW for each increase in Ta of 1C over 25C. 2 Power dissipation is reduced by 3.2mW for each increase in Ta of 1C over 25C. *Recommended operating conditions (unless otherwise noted, Ta = 25C) Parameter Recommend voltage Input voltage Output voltage Not designed for radiation resistance. Symbol VDD VIN VOUT Min. 4.5 0 0 Typ. 5.0 -- -- Max. 5.5 VDD VDD Unit V V V Conditions SIN, CK, LATCH, EN, RST SOUT 1 Standard ICs BU2114 / BU2114F *Logic circuit diagram 01 02 03 04 05 06 07 08 EN DQ CQB DQ CQB R DQ CQB R DQ CQB R DQ CQB R DQ CQB R DQ CQB R DQ CQB R LATCH R SIN DQ CQB DQ CQB R DQ CQB R DQ CQB R DQ CQB R DQ CQB R DQ CQB R DQ CQB R SOUT CK R RST *Pin assignments SIN CK LATCH SOUT EN RST GND GND GND VDD 01 02 03 04 05 06 07 08 Fig.1 2 Standard ICs BU2114 / BU2114F *Pin descriptions Pin No. 1 2 Symbol SIN CK I/O I I Serial data input pin Shift clock for shift register Setting this pin to "L" holds the latch output. While it is 3 LATCH I "H", latch output changes simultaneously when the shift register output changes. 4 SOUT O This is the output for the final-stage shift register. This is the Enable pin for O1 to O8. When this pin is "L", the latch output appears as is. 5 EN I When the output is "H", however, output QN is "L", and when the latch output is "L", Qn becomes HighZ 6 7 8 9 10 11 12 13 14 15 16 17 18 RST GND GND GND O8 O7 O6 O5 O4 O3 O2 O1 VDD I -- -- -- O O O O O O O O -- Resets the shift register and latch. 0V power supply 0V power supply 0V power supply Latch output for 8th stage of shift register Latch output for 7th stage of shift register Latch output for 6th stage of shift register Latch output for 5th stage of shift register Latch output for 4th stage of shift register Latch output for 3rd stage of shift register Latch output for 2nd stage of shift register Latch output for 1st stage of shift register + VDD power supply Function Note 1) O1 to O8 are open drain output, and when the shift register output is "H", the output level goes "L". 3 Standard ICs BU2114 / BU2114F *Electrical characteristics (unless otherwise noted, Ta = 25C, VDD = 5.0V) Parameter Input low level voltage Input high level voltage Output low level current Output high level current Schmitt trigger "H" threshold value Schmitt trigger "L" threshold value Schmitt trigger hysteresis width Output low level voltage Output leakage current Current dissipation Pull-up resistance Pull-down resistance Symbol VIL VIH ISL ISH VP VN VH VOL VOL Min. 0 Typ. -- -- -- -- -- -- 0.75 -- -- -- 1 50 50 Max. 1.5 5.0 6 -6 3.28 2.58 -- 0.15 0.4 10 100 68 68 Unit V V mA mA V V V V V A A k k Conditions SIN, LATCH, EN SIN, LATCH, EN SOUT (VL = 0.4) SOUT (VL = VDD - 0.4) CK, RST CK, RST CK, RST O1 ~ O8ID = 12mA O1 ~ O8ID = 36mA -- VDD or GND -- -- 3.5 -- -- 2.31 1.5 0.35 -- -- -- -- 35 35 IL IDD RUP RDN 4 Standard ICs BU2114 / BU2114F *Timing characteristics (unless otherwise noted, Ta = 25C, VDD = 5.0V) Parameter Clock frequency Clock pulse width Latch pulse width Data setup time Data hold time Clock latch time Symbol f tcw trw tsu th tdtl Conditions Input duty 50% -- -- CKSIN CKSIN -- 100 100 100 100 100 -- -- -- -- -- Min. Typ. Max. 5 -- -- -- -- -- Unit MHz ns ns ns ns ns 2.5V 2.5V SIN tsu th CK tcw tdtl LATCH trw Fig.2 Timing conditions 5 Standard ICs BU2114 / BU2114F *Switching characteristics (unless otherwise noted, Ta = 25C, VDD = 5.0V) Parameter Output "L - H" propagation time Input CK to output SOUT Output "H - L" propagation time Input CK to output SOUT Output "L - H" propagation time Input CK to output ON Output "H - L" propagation time Input CK to output ON Output "L - H" propagation time Input EN to output ON Output "H - L" propagation time Input EN to output ON Symbol Conditions tSLH tSPLH tOLH tOHL tELH tEHL Min. -- -- -- -- -- -- Typ. -- -- -- -- -- -- Max. 100 100 200 200 100 100 Unit ns ns ns ns ns ns VIH = 5v VIL = 0v CK tSLH tSLH SOUT EN tOLH tOHL tELH tEHL On Note) Measured with pull-up resistance of 1.0k and load of 20pF applied to terminals O1 to O8. Fig.3 Switching characteristic 6 Standard ICs BU2114 / BU2114F *Timing chart + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + CK RST SIN LATCH EN SOUT 01 02 03 04 05 06 07 08 Fig.4 * Input / output circuits 01 to 08 output SOUT output Pull-down input Pull-up input Fig.5 *Application example Expansion port 01 ~ 08 01 ~ 08 01 ~ 08 SIN BU2114 SOUT SIN BU2114 SOUT SIN BU2114 LATCH EN RST CK Fig.6 7 Standard ICs BU2114 / BU2114F *External dimensions (Units: mm) BU2114 22.9 0.3 18 10 6.5 0.3 BU2114F 11.2 0.2 18 7.8 0.3 5.4 0.2 10 1 0.51Min. 9 7.62 3.29 0.2 3.95 0.3 1 0.3 0.1 9 1.8 0.1 0.11 2.54 0.5 0.1 0 ~ 15 1.27 0.4 0.1 0.3Min. 0.15 DIP18 SOP18 8 0.15 0.1 |
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